A Hardware Accelerator for Elliptic Curve Cryptography

This paper describes a hardware accelerator for elliptic curve cryptography. The accelerator performs Galois field operations as a series of microcode instructions operating on 32-bit subsections of operands, which represent elements from GF(2) in a binary polynomial basis. The accelerator may be used for arbitrary size elliptic curves up to a field degree of 512. Parallelism between operations on the 32-bit subsections is exploited to increase performance. The accelerator uses a novel memory structure, a toggle-on-write register file, which incorporates Galois field addition and reduces the required number of register file read ports. The accelerator runs at 45 MHz on a Xilinx Virtex FPGA and takes 1.21ms to perform a 163-bit elliptic scalar multiplication. A 0.25 μm ASIC implementation of the accelerator was synthesized to run at 400 MHz and takes just 136μs to perform the same elliptic scalar multiplication.